1. Field of The Invention
The present invention relates generally to a connector/connecting technique for semiconductor devices. More specifically, the invention relates to a connector/connecting technique for use in a semiconductor memory required to be highly integrated.
2. Description of the Background Art
Referring now to the accompanying drawings, the prior art will be described. In recent years, with the miniaturization of semiconductor chips, a local interconnect has been used for connecting a gate electrode of a transistor to a diffusion layer. In particular, the local interconnect is effectively used for a semiconductor memory (SRAM) required to be highly integrated.
Referring to FIGS. 1A through 1D, a conventional method for forming a local interconnect and a contact will be described below.
First, as shown in FIG. 1A, a gate insulating film 3 and a gate electrode 4 are stacked on a semiconductor substrate 1. Then, as shown in FIG. 1B, the gate electrode 4 is used as a mask to form diffusion layers 2 serving as sources or drains on the semiconductor substrate 1 using the ion implantation. Subsequently, an interlayer insulating film 7 of silicon dioxide is formed on the whole surface using the CVD method. The interlayer insulating film 7 is deposited so as to have an elevation higher than that of the gate electrode 4. Then, as shown in FIG. 1C, the upper surface of the gate electrode 4 and the upper surfaces of one of the diffusion layers 2 are exposed to form an opening 7A by means of the photo-etching. Thereafter, as shown in FIG. 1D, an electrode material 9 is deposited on the inner surface of the opening 7A and the upper surface of the interlayer insulating film 7 using the sputtering or the like.
Then, as shown in FIG. 2A, the electrode material 9 on the interlayer insulating film 7 is removed by the CMP method. In the opening 7A, the gate electrode 4 is electrically connected to one of the diffusion layers 2 to form a local interconnect LIC. Subsequently, as shown in FIG. 2B, an interlayer insulating film 8 of silicon dioxide is deposited on the whole surface by the CVD method. Thereafter, as shown in FIG. 2C, a contact hole 10A is formed in the interlayer insulating films 7 and 8 so as to reach the diffusion layer 2 by means of the photo-etching. Subsequently, an electrode material 10 is embedded in the contact hole 10A, and an upper layer wiring 11 is formed thereon. By these steps, the local interconnect LIC and a contact CT are formed.
In a case where a local interconnect LIC and a contact CT are formed by the above described conventional method, the contact CT is formed (see FIGS. 2B through 2C) after the local interconnect LIC is formed (see FIGS. 1A through 2A). That is, the local interconnect structure and the contact are separately produced. Therefore, there is a problem in that the number of steps is high to complicate the manufacturing method and to increase the costs.